Supported MCU

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Supported MCU

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Features and peripherals counts

STM32F405xx and STM32F407xx
STM32F415xx and STM32F417xx

 

 

STM32F405xx and STM32F407xx

Peripherals

STM32F405RG

STM32F405OG

STM32F405VG

STM32F405ZG

STM32F405OE

STM32F407Vx

STM32F407Zx

STM32F407Ix

Flash memory in Kbytes

1024

512

512

1024

512

1024

512

1024

SRAM in Kbytes

System

192(112+16+64)

Backup

4

FSMC memory controller

No

Yes(1)

Ethernet

No

Yes

Timers

General-purpose

10

Advanced-control

2

Basic

2

IWDG

Yes

WWDG

Yes

RTC

Yes

Random number generator

Yes

Communication

interfaces

SPI / I2S

3/2 (full duplex)(2)

I2C

3

USART/UART

4/2

USB OTG FS

Yes

USB OTG HS

Yes

CAN

2

SDIO

Yes

Camera interface

No

Yes

GPIOs

51

72

82

114

72

82

114

140

12-bit ADC

Number of channels

3

16

13

16

24

13

16

24

24

12-bit DAC

Number of channels

Yes

2

Maximum CPU frequency

168 MHz

Operating voltage

1.8 to 3.6 V(3)

Operating temperatures

Ambient temperatures: –40 to +85 °C /–40 to +105 °C

Junction temperature: –40 to + 125 °C

Package

LQFP64

WLCSP90

LQFP100

LQFP144

WLCSP90

LQFP100

LQFP144

UFBGA176

LQFP176

1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.

2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.

3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 °C temperature range and an inverted reset signal is applied to PDR_ON.

source : STM32F405xxSTM32F407xx Datasheet (DOC ID 022152 Rev 3)

 

STM32F415xx and STM32F417xx

Peripherals

STM32F415RG

STM32F415OG

STM32F415VG

STM32F415ZG

STM32F417Vx

STM32F417Zx

STM32F417Ix

Flash memory in Kbytes

1024

512

1024

512

1024

512

1024

SRAM in Kbytes

System

192(112+16+64)

Backup

4

FSMC memory controller

No

Yes(1)

Ethernet

No

Yes

Timers

General-purpose

10

Advanced-control

2

Basic

2

IWDG

Yes

WWDG

Yes

RTC

Yes

Random number generator

Yes

Communication

interfaces

SPI / I2S

3/2 (full duplex)(2)

I2C

3

USART/UART

4/2

USB OTG FS

Yes

USB OTG HS

Yes

CAN

2

SDIO

Yes

Camera interface

No








GPIOs

51

72

82

114

82

114

140

12-bit ADC

Number of channels

3

16

13

16

24

16

24

24

12-bit DAC

Number of channels

Yes

2

Maximum CPU frequency

168 MHz

Operating voltage

1.8 to 3.6 V(3)

Operating temperatures

Ambient temperatures: –40 to +85 °C /–40 to +105 °C

Junction temperature: –40 to + 125 °C

Package

LQFP64

WLCSP90

LQFP100

LQFP144

LQFP100

LQFP144

UFBGA176

LQFP176

1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 °C temperature range and an inverted reset signal is applied to PDR_ON.

source : STM32F415xxSTM32F417xx Datasheet (DOC ID 022033 Rev 3)